Chris Lindsey

FPGA Engineering Portfolio

Digital design • Signal processing • Hardware development

Projects

A structured journey from HDL fundamentals to satellite signal decoding.

Phase 1: Foundations

Months 1–6 • Core HDL skills and basic hardware projects

01 Not Started

VGA/HDMI Test Pattern Generator

Video timing, ROM-based graphics, and TMDS encoding. Generates 720p/1080p output with selectable test patterns.

  • Video Timing
  • ROM
  • HDMI/TMDS
Details →
02 Not Started

UART Transceiver with FIFO

Bidirectional serial communication with configurable baud rates and TX/RX FIFOs.

  • Serial Protocols
  • FIFO Design
  • State Machines
Details →
03 Not Started

SPI Sensor Controller

Custom SPI master interfacing with accelerometer, gyroscope, and compass on the Blackboard.

  • SPI Protocol
  • Sensor Interface
  • State Machines
Details →

Phase 2: Intermediate Skills

Months 7–12 • DSP, VHDL, and Zynq ARM integration

04 Not Started

Digital Audio Equalizer

Real-time audio processing with FIR filters implementing a 3–5 band parametric equalizer.

  • DSP
  • FIR Filters
  • Fixed-Point
Details →
05 Not Started

Zynq Hardware Accelerator

Custom AXI peripheral controlled by ARM Cortex-A9, demonstrating hardware/software co-design.

  • AXI Protocol
  • PS-PL Integration
  • C++ Drivers
Details →

Phase 3: Advanced Projects

Months 13–18 • Software defined radio and ADS-B decoding

06 Not Started

ADS-B Aircraft Decoder

Complete 1090 MHz ADS-B receiver with real-time PPM demodulation and message parsing.

  • SDR
  • Demodulation
  • Protocol Implementation
Details →

Phase 4: Capstone

Months 19–24 • Satellite ground station

07 Not Started

Meteor M2 Satellite Image Decoder

Complete satellite ground station receiving and decoding weather images from polar-orbiting satellites. QPSK demodulation, Viterbi decoding, and LRPT protocol implementation.

  • QPSK
  • Viterbi FEC
  • Reed-Solomon
  • Complete System
Details →