UART Transceiver with FIFO
Bidirectional serial communication demonstrating protocol implementation skills.
Overview
Implement a complete UART transceiver with transmit and receive FIFOs. This project demonstrates understanding of serial protocols, asynchronous communication, and hardware buffer management.
The UART will support configurable baud rates and include status indicators for monitoring communication state.
Requirements
- Transmit and receive at configurable baud rates (9600 to 115200)
- Implement TX and RX FIFOs (minimum 16 bytes each)
- Echo received characters back to terminal
- Display received data on 7-segment display
- Status LEDs for TX busy, RX data available, FIFO full
Skills Demonstrated
- Serial Protocol Timing: Start bit, data bits, stop bit framing
- FIFO Design: Circular buffer with read/write pointers
- Baud Rate Generation: Clock divider from system clock
- Asynchronous Input Handling: Metastability synchronization
Deliverables
- GitHub repository with documented source code
- Block diagram showing TX, RX, and FIFO modules
- Testbench demonstrating various baud rates
- Demo showing terminal communication
- Resource utilization report
Architecture
Architecture will be documented as the project progresses.
Implementation Notes
Implementation notes will be added during development.
Resource Utilization
To be measured after implementation.
Progress Log
Not yet started
This project follows the VGA/HDMI Test Pattern Generator.