Zynq Hardware Accelerator

Overview

Create a custom hardware peripheral controlled by the Zynq's ARM Cortex-A9 processor, demonstrating the power of hybrid hardware/software system design. This project leverages the Zynq's unique PS-PL architecture.

The accelerator will demonstrate measurable performance improvement over a software-only implementation, showcasing effective hardware/software partitioning.

Requirements

• Custom AXI-Lite peripheral in VHDL or Verilog
• C/C++ driver running on Cortex-A9
• Demonstrate measurable speedup vs software-only implementation
• Suggested accelerators: image filter, CRC calculator, or encryption engine

Skills Demonstrated

• AXI Protocol: AXI-Lite interface implementation
• Hardware/Software Partitioning: Deciding what runs where
• Driver Development: C/C++ drivers for custom hardware
• Performance Optimization: Measurement and benchmarking

Prerequisites

This project requires understanding of:

• Zynq PS-PL architecture and AXI interfaces
• Creating custom AXI peripherals in Vivado
• Bare-metal C programming on Cortex-A9
• Memory-mapped register interfaces
• Interrupt handling between PS and PL

Study Resources

• The Zynq Book by Louise Crockett et al. (free PDF)
• Xilinx UG585: Zynq-7000 Technical Reference Manual

Architecture

Architecture will be documented as the project progresses.

Implementation Notes

Implementation notes will be added during development.

Resource Utilization

To be measured after implementation.

Progress Log