FPGA Logic Analyzer

Overview

Build an 8-channel logic analyzer with deep capture memory, serving as both a portfolio piece and a practical debugging tool for future projects. The analyzer uses the Tang Nano 20K's onboard SDRAM for 8M samples per channel and implements the SUMP protocol for compatibility with sigrok/PulseView software.

This project demonstrates SDRAM controller design, high-speed sampling, trigger logic, and RLE compression. A custom PCB with level shifters provides 5V tolerance for interfacing with various logic levels.

Specifications

Channels	8
Max Sample Rate	50-100 MHz
Capture Depth	8M samples per channel
Input Voltage	5V tolerant (via level shifters)
Trigger Modes	Edge, level, pattern match
Compression	Run-length encoding (RLE)
Host Protocol	SUMP (sigrok compatible)
Interface	USB via BL616

Requirements

• SDRAM controller for 64Mbit capture buffer
• Configurable sample rate (100Hz to 100MHz)
• Pre-trigger and post-trigger capture
• RLE compression for extended effective depth
• SUMP protocol implementation for sigrok compatibility
• Status LEDs (Armed, Triggered, Ready)

Skills Demonstrated

• SDRAM Controller: Memory interface design for high-bandwidth capture
• High-Speed Sampling: Clock domain crossing and data capture
• Trigger Logic: Pattern matching and edge detection
• RLE Compression: Data compression in hardware
• Protocol Implementation: SUMP protocol for host communication
• PCB Design: Custom breakout board with level shifters

Architecture

System block diagram:

Input Pins (8ch) → Level Shifters → FPGA GPIO
                                        ↓
                         Sampling Engine (50-100MHz)
                                        ↓
                            RLE Compression
                                        ↓
                         SDRAM Controller → 8MB SDRAM
                                        ↓
                          Trigger Engine
                                        ↓
                         BL616 (USB) → PC
                                        ↓
                             sigrok/PulseView

Hardware Build

Bill of Materials

Item	Est. Cost	Source
Tang Nano 20K	$25-35	Amazon/AliExpress
74LVC245 level shifters (x2)	$5	DigiKey/Mouser
2x5 pin header	$2	DigiKey/Mouser
LEDs + resistors	$3	DigiKey/Mouser
Custom PCB (JLCPCB)	$10-15	JLCPCB
3D printed enclosure	$5-10	Self-print
Probe wires/clips	$10	Amazon
Total	~$60-80

Custom PCB Requirements

• Tang Nano 20K mounting (socket or castellated)
• 8x level shifters (74LVC245 or similar) for 5V tolerance
• 2x5 0.1" probe header (8 signals + 2 grounds)
• Status LED connections
• Power filtering
• 3D printed enclosure

Resources

• openlogicbit - Reference Verilog implementation
• Open Bench Logic Sniffer - SUMP protocol reference
• sigrok Protocol Decoders - What the LA can decode
• Gowin SDRAM controller application notes
• Tang Nano 20K wiki and schematics

Deliverables

• GitHub repo with Verilog source
• KiCad PCB design files
• 3D enclosure STL files
• Testbench for each major module
• Video demo capturing SPI/UART from other projects
• sigrok/PulseView screenshots showing decoded protocols
• Hardware build photos

Implementation Notes

Implementation notes will be added during development.

Resource Utilization

To be measured after implementation.

Progress Log