UART Transceiver with FIFO

Overview

Implement a complete UART transceiver with transmit and receive FIFOs. This project demonstrates understanding of serial protocols, asynchronous communication, and hardware buffer management. The design will be implemented in both Verilog and VHDL to demonstrate dual-language proficiency.

The UART supports configurable baud rates and includes status indicators for monitoring communication state. This is the first portfolio project and establishes core skills for subsequent protocol implementations.

Requirements

• Transmit and receive at configurable baud rates (9600 to 115200)
• Implement TX and RX FIFOs (minimum 16 bytes each)
• Echo received characters back to terminal
• Display received data on 7-segment display
• Status LEDs for TX busy, RX data available, FIFO full
• Configurable data bits (7/8), parity (none/even/odd), stop bits (1/2)

Skills Demonstrated

• Serial Protocol Timing: Start bit, data bits, stop bit framing
• FIFO Design: Circular buffer with read/write pointers
• Baud Rate Generation: Clock divider from system clock
• Asynchronous Input Handling: Metastability synchronization
• Dual-Language Proficiency: Verilog and VHDL implementations

Deliverables

• GitHub repo with Verilog version
• GitHub repo with VHDL version (or same repo, separate branches)
• Testbench with simulation waveforms
• Video demo showing terminal communication
• Block diagram of architecture

Resources

• nandland.com UART tutorial
• Pong Chu's VHDL book chapters on UART
• Blackboard reference manual for pin constraints

Architecture

Architecture will be documented as the project progresses.

Implementation Notes

Implementation notes will be added during development.

Resource Utilization

To be measured after implementation.

Progress Log